1. Field of the Invention
The present invention relates to a semiconductor memory device. The device according to the present invention is used in the case where a simultaneous access by two sets of row/column addresses and a transfer of stored data between a pair of cell array units are carried out.
2. Description of the Related Arts
Today's semiconductor memory devices have an enormous capacity and are now used in many fields.
In general, a semiconductor memory device is comprised of a plurality of word lines and bit lines, a row decoder and a column decoder, both of which select word lines and bit lines, and a data bus (input/output port). That is, a one-cell-array-to-one-input/output-port structure is adopted.
Another modification is that a shift register is arranged in parallel with, for example, a DRAM (dynamic random access memory) cell array. In this memory device, data is transferred in parallel between the cell array and a shift register, a unit of n bits of data is input or output at an input/output port through said shift register, where the number of memory cells which belongs to one word line is N. On the other hand, a unit of one bit and the like of data is input or output at an input/output port at the side of a DRAM cell array.
A further modification is that two central processing units which have a common RAM are provided. In this case, the RAM should be accessable simultaneously and independently from the two input/output ports. Such a dual port RAM is realized by using a static random access memory (SRAM) device. That is, this dual port type RAM is provided with two sets of word lines and bit lines in a duplicate manner with respect to an SRAM cell array, and a word decoder and a column decoder is provided with each set, thus enabling a simultaneous and independent memory access.
It is difficult, however, for a dual port type SRAM to provide a cell array with duplicate word lines, bit lines, a word decoder, a column decoder, and the like. On the other hand, in the memory of a cell array plus shift register type DRAM, an access from the shift register side is composed of a unit of words and is not composed of a bit unit of a random access memory.